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zilog worldwide headquarters ? 532 race street ? san jose, ca 95126-3432 telephone: 408.558.8500 ? fax: 408.558.8300 ? www.zilog.com product specification ps014602-0103 z88c00 cmos super8 romless mcu
ps014602-0103 this publication is subject to replacement by a later edition. to determine whether a later edition exists, or to request copies of publications, contact: zilog worldwide headquarters 532 race street san jose, ca 95126-3432 telephone: 408.558.8500 fax: 408.558.8300 www.zilog.com windows is a registered trademark of microsoft corporation. document disclaimer ? 2003 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume li ability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. except with the express written approval zilog, use of information, devices, or technology as critical components of life support systems is not authorized. no licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
cmos super8 romless mcu product specification ps014602-0103 iii table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 protopack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 working register window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 mode and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 cpu program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 romless . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 rom and protopack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 cpu data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 instruction pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 condition codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 super-8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 service routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 fast interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 level or edge triggered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 stack operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 user-defined stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
cmos super8 romless mcu product specification ps014602-0103 iv dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 standard test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 input handshake timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 ac characteristics (20 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 input handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 output handshake timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ac characteristics (12 mhz, 20 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . 50 output handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ac characteristics (12 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 read /write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ac characteristics (20 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 read /write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 ac characteristics (20 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 eprom read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 example: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
cmos super8 romless mcu product specification ps014602-0103 v list of figures figure 1. pin assignments 88-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 2. pin assignments 44-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 3. pin assignments 48-pin dip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 4. pin functions 48-pin dip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 5. pin assignments 28-pin piggyback socket . . . . . . . . . . . . . . . . . . . . 4 figure 6. pin functions 28-pin piggyback socket . . . . . . . . . . . . . . . . . . . . . . 4 figure 7. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 8. super8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 9. working register window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 10. mode and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11. mode and control registers (continued) . . . . . . . . . . . . . . . . . . . . 13 figure 12. mode and control registers (continued) . . . . . . . . . . . . . . . . . . . . . 14 figure 13. mode and control registers (continued) . . . . . . . . . . . . . . . . . . . . 15 figure 14. mode and control registers (continued) . . . . . . . . . . . . . . . . . . . . 16 figure 15. mode and control registers (continued) . . . . . . . . . . . . . . . . . . . . . 17 figure 16. program and data memory address spaces . . . . . . . . . . . . . . . . . 23 figure 17. instruction formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 18. instruction formats (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 19. opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 20. interrupt levels and vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 21. standard test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 22. fully interlocked mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 23. strobed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 24. fully interlocked mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 25. strobed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 26. external memory read and write timing. . . . . . . . . . . . . . . . . . . . . 53 figure 27. eprom read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 28. 44-pin plcc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 29. 48-pin dip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
cmos super8 romless mcu product specification ps014602-0103 vi list of tables table 1. super-8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2. port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3. pin assignments for ports 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4. condition codes and meanings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 5. instruction set notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 6. instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7. second nibble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 8. super8 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 9. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 10. ac characteristics (20 mhz) input handshake . . . . . . . . . . . . . . . . . 49 table 11. ac characteristics (12 mhz, 20 mhz) output handshake . . . . . . . . 50 table 12. ac characteristics (12 mhz) read/write . . . . . . . . . . . . . . . . . . . . . 51 table 13. ac characteristics (20 mhz) read/write. . . . . . . . . . . . . . . . . . . . . . 52 table 14. ac characteristics (20 mhz) eprom read cycle . . . . . . . . . . . . . . 54
cmos super8 romless mcu product specification ps014602-0103 features 1 features ? improved z8? instruction set includes multiply and divide instructions, boolean and bcd operations. ? additional instructions support threaded-code languages, such as "forth." ? 325 byte registers, including 272 general-purpose registers, and 53 mode and control registers. ? addressing of up to 128k bytes of memory. two register pointers allow use of short and fast instructions to access register groups within 600 nsec. ? direct memory access controller (dma). ? two 16-bit counter/timers. ? up to 32 bit-programmable and 8 byte-programmable i/o lines, with 2 handshake channels. ? interrupt structure supports: ? 27 interrupt sources ? 16 interrupt vectors (2 reserved for future versions) ? 8 interrupt levels ? servicing in 600 nsec. (1 level only) ? full-duplex uart with special features. ? on-chip oscillator. ? 20 mhz clock. ? 8k byte rom for z8820 general description the zilog super8 single-chip mcu can be used for development and production. it can be used as i/o- or memory-intensive computers, or configured to address external memory while still supporting many i/o lines.
cmos super8 romless mcu product specification ps014602-0103 general description 2 figure 1.pin assignments 88-pin plcc the super8 features a full-duplex universal asynchronous receiver/ transmitter (uart) with on-chip baud rate generator, two programmable counter/timers, a direct memory access (dma) controller, and an on-chip oscillator. the super8 is also available as a 48-pi n and 68-pin romless microcomputer with four byte-wide i/o ports plus a byte-wide address/data bus. additional address bits can be configured, up to a total of 16. figure 2.pin assignments 44-pin plcc nc nc nc nc nc n c nc n c n c v cc v cc v cc nc n c n c n c gnd gnd gnd g n d v cc xtal2 xtal1 romless rese t r/w po 8 po 7 p3 4 p3 5 p4 0 p4 1 p4 2 p4 3 p4 4 p4 5 p4 6 p4 7 p1 6 p1 7 p2 4 p2 5 p1 5 p1 4 p1 3 p1 2 p 1 1 p1 0 p0 0 p0 1 p0 2 po 3 p0 4 p2 2 p 0 5 p 3 2 p 3 3 p2 3 p 2 0 p2 1 p 3 1 p 3 0 p2 6 p27 p37 p3 6 as ds 68 67 66 65 64 63 62 61 93 84 5 76 21 60 59 58 57 56 55 53 54 52 51 50 49 48 47 46 45 44 10 11 12 13 14 21 22 23 24 25 26 15 16 17 18 19 20 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 super8 p05 vcc p06 p07 p34 p35 ds as gnd r/w reset 29 28 p16 p25 p17 p24 vcc gnd p22 p47 xtal2 xtal1 romless p15 p14 p13 p12 p11 p10 p00 p01 p02 p03 p04 p33 p32 p23 p20 p21 p30 p31 p26 p76 p37 p27 z8801 18 19 20 21 22 23 24 25 26 27 44 43 42 41 40 39 17 6 5 4 3 2 1 7 8 9 10 11 12 13 14 15 16 38 37 36 35 34 33 32 31 30
cmos super8 romless mcu product specification ps014602-0103 general description 3 figure 3.pin assignments 48-pin dip figure 4.pin functions 48-pin dip p1 0 p1 1 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 p2 4 p2 5 p4 4 p4 5 p4 6 p4 7 p2 2 p3 2 p3 3 p2 3 p2 0 p2 1 p3 1 +5v xtal2 xtal1 p0 0 p0 1 p0 2 p0 3 p0 4 p0 5 p0 6 p0 7 p3 4 p3 5 p4 1 gnd p4 2 p4 3 r/w reset p3 6 p3 7 p2 7 p2 6 p3 0 as ds p4 0 super8 11 34 13 12 22 23 18 21 9 10 26 27 25 24 19 20 40 39 29 28 14 15 16 17 30 31 37 38 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 36 35 33 32 reset r/w ds as p0 0 p0 1 p0 2 p0 3 p0 4 p0 5 p0 6 p0 7 p1 0 p1 1 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 p4 0 p4 1 p4 2 p4 3 +5v gnd xtal1 xtal2 p4 4 p4 5 p4 6 p4 7 p2 0 p2 1 p2 2 p2 3 p2 4 p2 5 p2 6 p2 7 p3 0 p3 1 p3 2 p3 3 p3 4 p3 5 p3 6 p3 7 power clock port 2 port 3 port 4 (1/2) port 4 (1/2) port 1 port 0 timing and control super8
cmos super8 romless mcu product specification ps014602-0103 general description 4 figure 5.pin assignments 28-pin piggyback socket figure 6.pin functions 28-pin piggyback socket protopack this part functions as an emulator for the basic microcomputer. it uses the same package and pin-out as the basic microcomputer but also has a 28-pin "piggy back" socket on the top into which a rom or eprom can be installed. the socket is designed to accept a type 2764 eprom. this package permits the protopack to be used in prototype and final pc boards while still permitting user program development. when a final program is devel- +5 +5 d 4 a 11 a 9 a 8 a 13 d 3 d 6 d 5 d 7 a 10 oe ce +5 a 12 d 2 a 4 a 5 a 6 a 7 gnd d 0 d 1 a 0 a 2 a 3 a 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 proto- pack eprom socket d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 oe ce gnd +5v +5v +5v a 0 a 1 a 2 a 5 a 3 a 4 a 13 a 6 a 7 a 8 a 11 a 9 a 10 a 12 address data gnd power protopack eprom socket
cmos super8 romless mcu product specification ps014602-0103 architecture 5 oped, it can be mask-programmed into the production microcomputer device, directly replacing the emulator. the protopack part is also useful in situations where the cost of mask-programming is prohibitive or where program flexibility is desired. figure 7.functional block diagram architecture the super8 architecture includes 325 byte-wide internal registers. 272 of these are available for general purpose use; the remaining 53 provide control and mode functions. the instruction set is specially designed to deal with this large register set. it includes a full complement of 8-bit arithmetic and logical operations, including multiply and divide instructions and provisions for bcd operations. addresses and counters can be incremented and decremented as 16-bit quantities. rotate, shift, and bit manipulation instructions are provided. three new instructions support threaded-code languages. the uart is a full-function multipurpose asynchro- nous serial channel with many premium features. i/o (bit programmable) port 4 dma alu flags pointers register uart counter/ timers (2) register file 272 x 8-bit machine timing and instruction control z8822 eprom interface program counter port 1 port 0 port 2 port 3 xtal as ds r/w reset address data 14 8 i/o (bit programmable or control) 2-bus when uses as address/data bus address or i/o (bit programmable) address/data or i/o (byte programmable) 8 interrupt control
cmos super8 romless mcu product specification ps014602-0103 pin descriptions 6 the 16-bit counters can operate independently or be cascaded to perform 32-bit counting and timing operations. the dma controller handles transfers to and from the register file or memory. dma can use the uart or one of two ports with hand- shake capability. the architecture appears in the block diagram (figure 7). pin descriptions the super8 connects to external devices via the following ttl-compatible pins: as . address strobe (output, active low). as is pulsed low once at the beginning of each machine cycle. the rising edge indicates that addresses r/w and dm , when used, are valid. ds . data strobe (output, active low). ds provides timing for data movement between the address/data bus and external memory. during write cycles, data output is valid at the leading edge of ds . during read cycles, data input must be valid prior to the trailing edge of ds . p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 . port i/o lines (input/output). these 40 lines are divided into five 8-bit i/o ports that can be configured under program control for i/o or external memory interface. in the romless devices, port 1 is dedicated as a multiplexed address/data port, and port 0 pins can be assigned as additional address lines; port 0 non-address pins may be assigned as i/o. in the rom and protopack, port 1 can be assigned as input or output, and port 0 can be assigned as input or output on a bit by bit basis. ports 2 and 3 can be assigned on a bit-for-bit basis as general i/o or interrupt lines. they can also be used as special-purpose i/o lines to support the uart, counter/timers, or handshake channels. port 4 is used for general i/o. during reset, all port pins are configured as inputs (high impedance) except for port 1 and port 0 in the romless devices. in these, port 1 is configured as a mul- tiplexed address/data bus, and port 0 pins po 0 -po 4 are configured as address out, while pins p0 5 -po 7 are configured as inputs. reset . reset (input, active low). reset initializes and starts the super8. when it is activated, it halts all processing; when it is deactivated, the super8 begins pro- cessing at address 0020h. romless . (input, active high). this input controls the operation mode of a 68-pin super8. when connected to vcc, the part functions as a romless z8800. when connected to gnd, the part functions as a z8820 rom part.
cmos super8 romless mcu product specification ps014602-0103 registers 7 r/w . readlwrite (output). r/w determines the direction of data transfer for exter- nal memory transactions. it is low when writing to program memory or data mem- ory, and high for everything else. xtal1, xtal2 . (crystal oscillator input.) these pins connect a parallel resonant crystal or an external clock source to the on-board clock oscillator and buffer. registers the super8 contains a 256-byte internal register space. however, by using the upper 64 bytes of the register space more than once, a total of 325 registers are available. registers from 00 to bf are used only once. they can be accessed by any regis- ter command. register addresses c0 to ff contain two separate sets of 64 regis- ters. one set, called control registers, can only be accessed by register direct commands. the other set can only be addressed by register indirect, indexed, stack, and dma commands. the uppermost 32 register direct registers (e0 to ff) are further divided into two banks (0 and 1), selected by the bank select bit in the flag register. when a reg- ister direct command accesses a register between e0 and ff, it looks at the bank select bit in the flag register to select one of the banks. the register space is shown in figure 8.
cmos super8 romless mcu product specification ps014602-0103 registers 8 figure 8.super8 registers working register window control registers r214 and r215 are the r egister pointers, rpo and rp1. they each define a moveable, 8-register section of the register space. the registers within these spaces are called working registers. working registers can be accessed using short 4-bit addresses. the process, shown in section a of figure 9, works as follows: ? the high-order bit of the 4-bit address selects one of the two register pointers (0 selects rpo; 1 selects rp1). ? the five high-order bits in the register pointer select an 8-register (contiguous) slice of the register space. ? the three low-order bits of the 4-bit address select one of the eight registers in the slice. the net effect is to concatenate the five bits from the register pointer to the three bits from the address to form an 8-bit address. as long as the address in the regis- ff h eo h df h cf h co h do h bank1 bank0 ff h bf h oo h 192 bytes 256 bytes data registers (indirect register, indexed, stack or dma access only) co h data registers (all addressing modes) set one set two mode and control registers (register addressing only) system registers: stack, flags, ports, etc. (register addressing only) working registers (working register addressing only)
cmos super8 romless mcu product specification ps014602-0103 registers 9 ter pointer remains unchanged, the three bits from the address always point to an address within the same eight registers. the register pointers can be moved by changing the five high bits in control regis- ters r214 for rp0 and r215 for rp1. the working registers can also be accessed by using full 8-bit addressing. when an 8-bit logical address in the range 192 to 207 (co to cf) is specified, the lower nibble is used similarly to the 4-bit addressing described above. this is shown in section b of figure 9. figure 9.working register window since any direct access to logical addresses 192 to 207 involves the register pointers, the physical registers 192 to 207 can be accessed only when selected by a register pointer. after a reset, rpo points to r192 and rp1 points to r200. register list super-8 registers lists the super8 registers. for more details, see figure 10. register pointer provides 5 low-order bits address selects rp0 or rp1 rp0 (r214) rp1 (r215) 8-bit logical address 3 low-order bits 1 1 0 0 8-bit physical address b. 8-bit addressing selects rp0 or rp1 register pointer provides 5 high-order bits together they create 8-bit register address a. 4-bit addressing address opcode 4-bit addess provides 3 low-order bits rp0 (r214) rp1 (r215)
cmos super8 romless mcu product specification ps014602-0103 registers 10 table 15.super-8 registers address mnemonic function decimal hexadecimal general-purpose registers 000-192 00-bf - general purpose (all address modes) 192-207 c0-cf - working register (direct only) 192-255 c0-ff - general purpose (indirect only) mode and control registers 208 d0 p0 port 0 i/o bits 209 di p1 port 1 (i/o only) 210 d2 p2 port 2 211 d3 p3 port 3 212 d4 p4 port 4 213 d5 flags system flags register 214 d6 rp0 register pointer 0 215 d7 rp1 register pointer 1 216 d8 sph stack pointer high byte 217 d9 spl stack pointer low byte 218 da iph instruction pointer high byte 219 db ipl instruction pointer low byte 220 dc irq interrupt request 221 dd imr interrupt mask register 222 de sym system mode 224 e0 bank 0 c0ct ctr 0 control bank 1 com ctr 0 mode 225 e1 bank 0 c1ct ctr 1 control bank 1 c1m ctr 1 mode 226 e2 bank 0 c0ch ctr 0 capture register, bits 8-15 bank 1 ctch ctr 0 timer constant, bits 8-15 227 e3 bank 0 c0cl ctr 0 capture register, bits 0-7
cmos super8 romless mcu product specification ps014602-0103 registers 11 bank 1 ctcl ctr 0 time constant, bits 0-7 228 e4 bank 0 c1ch ctr 1 capture register, bits 8-15 bank 1 c1tch ctr 1 time constant, bits 8-15 229 e5 bank 0 c1cl ctr 1 capture register, bits 0-7 bank 1 c1tcl ctr 1 time constant, bits 0-7 235 eb bank 0 utc uart transmit control 236 ec bank 0 urc uart receive control 237 ed bank 0 uie uart interrupt enable 239 ef bank 0 uio uart data 240 f0 bank 0 pom port 0 mode bank 1 dch dma count, bits 8-15 241 f1 bank 0 pm port mode register bank 1 dcl dma count, bits 0-7 244 f4 bank 0 hoc handshake channel 0 control 245 f5 bank 0 h1c handshake channel i control 246 f6 bank 0 p4d port 4 direction 247 f7 bank 0 p40d port 4 open drain 248 f8 bank 0 p2am port 2/3 a mode bank 1 ubgh uart baud rate generator, bits 8-15 249 f9 bank 0 p2bm port 2/3 b mode bank 1 ubgl uart baud rate generator, bits 0-7 250 fa bank 0 p2cm port 2/3 c mode bank 1 uma uart mode a 251 fb bank 0 p2dm port 2/3 d mode bank 1 umb uart mode b 252 fc bank 0 p2aip port 2/3 a interrupt pending 253 fd bank 0 p2bip port 2/3 b interrupt pending 254 fe bank 0 emt external memory timing table 15.super-8 registers (continued) address mnemonic function decimal hexadecimal
cmos super8 romless mcu product specification ps014602-0103 mode and control registers 12 mode and control registers figure 10.mode and control registers bank 1 wumch wakeup match register 255 ff bank 0 ipr interrupt priority register bank 1 wumsk wakeup match register table 15.super-8 registers (continued) address mnemonic function decimal hexadecimal d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r216 (d8) sph stack pointer d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r215 (d7) rp1 register pointer 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r214 (d6) rp0 register pointer 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r213 (d5) flags system flags register d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r217 (d9) spl stack pointer carry flag zero flag sign flag overflow flag bank address fast interrupt status half-carry flag decimal adjust (rp3?rp7) not used (rp3?rp7) not used high byte (sp8?sp15) low byte (sp0?sp7) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r221 (dd) imr interrupt mask level 7 level 6 level 1 level 5 level 4 level 3 level 2 level 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r220 (dc) irq interrupt request (read only) level 7 level 6 level 1 level 5 level 4 level 3 level 2 level 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r218 (da) iph instruction pointe high high byte (ip8?ip15) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r219 (db) ipl instruction pointer low low byte (ip0?ip7)
cmos super8 romless mcu product specification ps014602-0103 mode and control registers 13 figure 11.mode and control registers (continued) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r224 bank 1 (e0) c0m counter 0 mode d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r222 (de) sym system mode 000 not used capture mode fast interrupt select 1 = fast interrupt enable 1 = global interrupt enable d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r224, bank 0 (e0) c0ct counter 0 control 001 010 011 100 001 110 111 level 0 level 1 level 2 level 3 level 4 level 5 level 6 level 7 1 = enable counter read 1 = end of count write 1 = reset end of count 1 = zero count interrupt enable 1 = software capture 1 = software trigger 0 = single cycle 1 = continuous 0 = count down 1 = count up 1 = load counter 00 = no capture 01 = capture on rising 10 = bi-value mode 0 = external up/down control p2 7 1 = programmed up/down control 1 = enable retrigger d 7 d 6 d 5 d 4 p2 7 p2 6 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 input pin assignments ?undefined? ?undefined? ? cascade counters? i/o i/o i/o i/o i/o gate gate trigger gate gate/ trigger c0 output c0 output c0 output c0 output c0 output trigger trigger trigger i/o c0 output c0 output c0 output c0 output c0 output gate gate/trigger 1 = software trigger d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r225, bank 0 (e1) c1ct counter 1 control 1 = enable counter read 1 = end of count 1 = zero count interrupt enable 1 = software capture 0 = single cycle 0 = count down 1 = count up 1 = load counter 1 = continuous write 1 = reset end of count edge of p2 7 11 = capture on both edges of p2 7
cmos super8 romless mcu product specification ps014602-0103 mode and control registers 14 figure 12.mode and control registers (continued) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r225 bank 1 (e1) c1m counter 1 mode d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r228 bank 1 (e4) c1tch counter 1 time constant d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r236 bank 0 (ec) urc uart receive control 1 = receive character 1 = parity error 1 = receive enable 01 = capture on rising edge of p3 7 11 = capture on both edges of p3 7 10 = bi-value mode 0 = external up/down control p3 7 1 = programmed up/down control 1 = enable retrigger d 7 d 6 d 5 d 4 p3 7 p3 6 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 input pin assignments ?undefined? ?undefined? ?undefined? i/o i/o i/o i/o i/o gate gate trigger gate gate/ trigger c0 output c0 output c0 output c0 output c0 output trigger trigger trigger i/o c0 input c0 input c0 input c0 input c0 output gate gate/trigger 00 = no capture capture mode high byte (c1tc 8 ?c1tc 15 ) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r228 bank 0 (e4) c1ch counter 1 capture high byte (c1c 8 ?c1c 15 ) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r227 bank 1 (e4) c0tcl counter 0 time constant low byte (c0tc 0 ?c0tc 7 ) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r227 bank 0 (e3) c0cl counter 0 capture low byte (c0tc 0 ?c1tc 7 ) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r226 bank 1 (e2) c0tch counter 0 time constant high byte (c0tc 8 ?c0tc 15 ) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r226 bank 0 (e2) c0ch counter 0 capture high byte (c0c 8 ?c0c 15 ) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r229 bank 0 (e5) c1cl counter 1 capture low byte (c1c 0 ?c1c 7 ) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r229 bank 1 (e5) c1tcl counter 1 time constant low byte (c1tc 0 ?c1tc 7 ) available 1 = overrun error 1 = wake-up detect 1 = break detect 1 = control character detect 1 = framing error d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r235 bank 0 (e8) utc uart transmit control 1 = transmit dma enable 1 = zero count 1 = transmit buffer empty 1 = transmit enable transmit data select 0 = output p3 1 data 1 = output transmit data 1 = send break stop bits: 0 = 1 stop bit 1 = 2 stop bits 1 = wake-up enable
cmos super8 romless mcu product specification ps014602-0103 mode and control registers 15 figure 13. mode and control registers (continued) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r237 bank 0 (ed) uie uart interrupt enable 1 = receive character 1 = transmit interrupt enable 1 = receive dma enable available interrupt enable 1 = zero count interrupt enable 1 = wake-up interrupt enable 1 = break interrupt enable 1 = control character 1 = receive error interrupt interrupt enable enable d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r240 bank 0 (f0) p0m port 0 mode p0 0 mode p0 2 mode p0 1 mode p0 3 mode p0 7 mode p0 5 mode p0 6 mode p0 4 mode 0 = i/o; 1 = address d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r229 bank 0 (ef) uio uart receive data (read) data (d 0 = lsb) uart transmit data (write) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r240 bank 1 (f0) dch high byte (dc 8 -dc 15 ) dma count d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r246 bank 0 (f6) p4d p4 0 -p4 7 i/o direction port 4 direction 0 = output; 1 = input d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r247 bank 0 (f7) p4od p4 0 -p4 7 open-drain port 4 open-drain 0 = push-pull; 1 = open-drain d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r245 bank 0 (f5) h1c handshake 1 control (write only) 1 = handshake enable mode: not used 1 = fully interlocked deskew counter (range 1-16) 0 = strobed d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r244 bank 0 (f4) h0c handshake 0 control (write only) 1 = handshake enable mode: 1 = fully interlocked deskew counter (range 1-16) 0 = strobed 1 = port 1; 0 = port 4 port select: dma enable: 1 = enabled 0 = disabled d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r241 bank 1 (f1) dcl low byte (dc 0 -dc 7 ) dma count d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r248 bank 0 (f8) p2am port 2/3 a mode (write only) 00 input 01 input, interrupt enabled 10 output, push-pull p3 1 mode d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r241 bank 0 (f1) pm port mode (write only) 1 = input 00 port 1 mode output 0 = output port 0 direction 01 input 0x address/data not used 0 = output 1 = open-drain 0 = push-pull open-drain port 0 0 = 1 = open-drain 0 = push-pull open-drain port 1 0 = 1 = enable 0 = disable enable dm p3 5 0 = p3 0 mode p2 0 mode p2 1 mode 11 output, open-drain
cmos super8 romless mcu product specification ps014602-0103 mode and control registers 16 figure 14.mode and control registers (continued) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r248 bank 1 (f8 ubgh uart baud rate generator high byte (ubgh 8 ?ubgh 15 ) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r249 bank 1 (f9) ubgl uart baud rate generator low byte (ubg 0 ?ubg 7 ) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r250 bank 0 (fa) p2cm port 2/3 c mode (write only) 00 input 01 input, interrupt enabled 10 output, push-pull p3 5 mode p3 4 mode p2 4 mode p2 5 mode 11 output, open-drain d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r251 bank 0 (fb) p2dm port 2/3 d mode (write only) 00 input 01 input, interrupt enabled 10 output, push-pull p3 7 mode p3 6 mode p2 6 mode p2 7 mode 11 output, open-drain d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r249 bank 0 (f9) p2bm port 2/3 b mode (write only) 00 input 01 input, interrupt enabled 10 output, push-pull p3 3 mode p3 2 mode p2 2 mode p2 3 mode 11 output, open-drain d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r251 bank 1 (fb) umb uart mode b 1 = loopback enable 1 = baud-rate generator enable 0 0 d 7 d 6 = p2 1 data 0 1 = system clock (xtal2) 1 0 = baud-rate generator output 1 1 = transmit data clock receive clock input select: clock output select d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r250 bank 1 (fa) uma uart mode a transmit wake-up value 1 = even parity receive wake-up value 1 = parity enable 0 0 d 5 d 4 = x1 0 1 = x16 1 0 = x32 1 1 = x64 0 0 d 7 d 6 = 5 bits 0 1 = 6 bits 1 0 = 7 bits 1 1 = 8 bits bits per character clock rate 1 = auto-echo 0 = p2 0 1 = baud-rate generator output baud-rate generator source: 0 = p2 0 (external) 1 = internal (xtal/4) transmit clock input select: 0 = p2 1 1 = baud-rate generator output
cmos super8 romless mcu product specification ps014602-0103 i/o ports 17 figure 15.mode and control registers (continued) i/o ports the super8 has 40 i/o lines arranged into five 8-bit ports. these lines are all ttl- compatible, and can be configured as inputs or outputs. some can also be config- ured as address/data lines. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r255 bank 1 (ff) wumsk wake-up match register these bits correspond to bits d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r254 bank 0 (fe) emt external memory timing register stack select: 0 = register file 1 = data memory data memory automatic waits 00 = no waits 10 = 1 wait d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r252 bank 0 (fc) p2aip port 2/3 a interrupt pending (read only) p2 0 p3 0 p2 1 p3 1 p3 4 p2 3 p3 2 p2 2 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r253 bank 0 (fd) p2 bip port 2/3 b interrupt pending (read only) p2 4 p3 4 p2 5 p3 5 p3 7 p2 7 p3 6 p2 6 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r254 bank 1 (fe) wumch wake-up match register this byte, minus masked bits, slow memory timing 0 = disabled 1 = enabled program memory automatic waits 00 = no waiits 01 = 1 wait dma select: 0 = register file 1 = data memory d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r255 bank 0 (ff) ipr interrupt priority register d 7 d 4 d 1 group priority group b 0 = irq2 > (irq3, irq4) 1 = (irq3, irq4) > irq2 subgroup b 0 = irq3 > irq4 1 = irq4 > irq3 subgroup c 0 = irq6 > irq7 1 = irq7 > irq6 group c 0 = irq5 > (irq6, irq7) 1 = (irq6, irq7) > irq5 group a 0 = irq0 > irq1 1 = irq1 > irq0 0 0 0 = undefined 0 0 1 = b > c > a 0 1 0 = a > b > c 0 1 1 = b > a > c 1 0 0 = c > a > b 1 0 1 = c > b > a 1 1 0 = a > c > b 1 1 1 = undefined external wait input 0 =p3 4 is normal i/o 1 =p3 4 is external wait input 10 = 2 waits 11 = 3 wai ts is used for wake-up match in wake-up match register; 0s mask corresponding match bits 10 = 2 waits 11 = 3 wai ts
cmos super8 romless mcu product specification ps014602-0103 i/o ports 18 each port has an input register, an output register, and a register address. data coming into the port is stored in the input register, and data to be written to a port is stored in the output register. reading a port?s register address returns the value in the input register; writing a port?s register address loads the value in the output register. if the port is configured for an output, this value appears on the external pins. when the cpu reads the bits configured as outputs, the data on the external pins is returned. under normal output loading, this has the same effect as reading the output register, unless the bits are configured as open-drain outputs. the ports can be configured as shown in table 2, port configuration. port 0 port 0 can be configured as an i/o port or an output for addressing external mem- ory, or it can be divided and used as both. the bits configured as i/o can be either all outputs or all inputs; they cannot be mixed. if configured for outputs, they can be push-pull or open-drain type. any bits configured for i/o can be accessed via r208. to write to the port, specify r208 as the destination (dst) of an instruction; to read the port, specify r208 as the source (src). port 0 bits configured as i/o can be placed under handshake control of hand- shake channel 1. port 0 bits configured as address outputs cannot be accessed via the register. in romless devices, initially the four lower bits are configured as address eight through twelve. table 16.port configuration port configuration choices 0 address outputs and/or general i/o 1 multiplexed address/data (or i/o, only for rom and protopack) 2 and 3 control i/o for uart, handshake channels, and counter/timers; also general i/o and external interrupts 4 general i/o
cmos super8 romless mcu product specification ps014602-0103 i/o ports 19 port 1 in the romless device, port 1 is configured as a byte-wide address/data port. it provides a byte-wide multiplexed address/data path. additional address lines can be added by configuring port 0. the rom and protopack port 1 can be configured as above or as an i/o port; it can be a byte-wide input, open-drain output, or push-pull output. it can be placed under handshake control or handshake channel 0. ports 2 and 3 ports 2 and 3 provide external control inputs and outputs for the uart, hand- shake channels, and counter/timers. the pin assignments appear in table 3. bits not used for control i/o can be configured as general-purpose i/o lines and/or external interrupt inputs. those bits configured for general i/o can be configured individually for input or output. those configured for output can be individually configured for open-drain or push-pull output. all port 2 and 3 input pins are schmitt-triggered. the port address for port 2 is r210, and for port 3 is r211. table 17.pin assignments for ports 2 and 3 port 2 port 3 bit function bit function 0 uart receive clock 0 uart receive data 1 uart transmit clock 1 uart transmit data 2 reserved 2 reserved 3 reserved 3 reserved 4 handshake 0 input 4 handshake 1 input/wait 5 handshake 0 output 5 handshake 1 output/dm 6 counter 0 input 6 counter 1 input 7 counter 0 i/o 7 counter 1 i/o
cmos super8 romless mcu product specification ps014602-0103 i/o ports 20 port 4 port 4 can be configured as i/o only. each bit can be configured individually as input or output, with either push-pull or open-drain outputs. all port 4 inputs are schmitt-triggered. port 4 can be placed under handshake control of handshake channel 0. its regis- ter address is r212. uart the uart is a full-duplex asynchronous channel. it transmits and receives inde- pendently with 5 to 8 bits per character, has options for even or odd bit parity, and a wake-up feature. data can be read into or out of the uart via r239, bank 0. this single address is able to serve a full-duplex channel because it contains two complete 8-bit regis- ters-one for the transmitter and the other for the receiver. pins the uart uses the following port 2 and 3 pins: port/pin uart function 2/0 receive clock 3/0 receive data 2/1 transmit clock 3/1 transmit data transmitter when the uart?s register address is specified as the destination (dst) of an oper- ation, the data is output on the uart, which automatically adds the start bit, the programmed parity bit, and the programmed number of stop bits. it can also add a wake-up bit if that option is selected. if the uart is programmed for a 5-, 6-, or 7-bit character, the extra bits in r239 are ignored. serial data is transmitted at a rate equal to 1, 1/16, 1/32 or 1/64 of the transmitter clock rate, depending on the programmed data rate. all data is sent out on the fall- ing edge of the clock input.
cmos super8 romless mcu product specification ps014602-0103 address space 21 when the uart has no data to send, it holds the output marking (high). it may be programmed with the send break command to hold the output low (spacing), which it continues until the command is cleared. receiver the uart begins receive operation when receive enable (urc, bit 0) is set high. after this, a low on the receive input pin for longer than half a bit time is interpreted as a start bit. the uart samples the data on the input pin in the mid- dle of each clock cycle until a complete byte is assembled. this is placed in the receive data register. if the 1 x clock mode is selected, external bit synchronization must be provided, and the input data is sampled on the rising edge of the clock. for character lengths of less than eight bits, the uart inserts ones into the unused bits, and, if parity is enabled, the parity bit is not stripped. the data bits, extra ones, and the parity bit are placed in the uart data register (uio). while the uart is assembling a byte in its input shift register, the cpu has time to service an interrupt and manipulate the data character in uio. once a complete character is assembled, the uart checks it and performs the following: ? if it is an-ascii control character, the uart sets the control character status bit. ? it checks the wake-up settings and completes any indicated action. ? if parity is enabled, the uart checks to see if the calculated parity matches the programmed parity bit. if they do not match, it sets the parity error bit in urc (r236 bank 0), which remains set until reset by software. ? it sets the framing error bit (urc, bit 4) if the character is assembled without any stop bits. this bit remains set until cleared by software. overrun errors occur when characters are received faster than they are read. that is, when the uart has assembled a complete character before the cpu has read the current character, the uart sets the overrun error bit (urc, bit 3), and the character currently in the receive buffer is lost. the overrun bit remains set until cleared by software. address space the super8 can access 64k bytes of program memory and 64k bytes of data memory. these spaces can be either combined or separate. if separate, they are
cmos super8 romless mcu product specification ps014602-0103 address space 22 controlled by the dm line (port p3 5 ), which selects data memory when low and program memory when high. figure 16 on page 23 shows the system memory space. cpu program memory program memory occupies addresses 0 to 64k. external program memory, if present, is accessed by configuring ports 0 and 1 as a memory interface. the address/data lines are controlled by as , ds and r/w . the first 32 program memory bytes are reserved for interrupt vectors; the lowest address available for user programs is 32 (decimal). this value is automatically loaded into the program counter after a hardware reset. romless port 0 can be configured to provide from 0 to 8 additional address lines. port 1 is always used as an 8-bit multiplexed address/data port. rom and protopack port 1 is configured as multiplexed address/data or as i/o. when port 1 is config- ured as address/data, port 0 lines can be used as additional address lines, up to address 15. external program memory is mapped above internal program mem- ory; that is, external program memory can occupy any space beginning at the top of the internal rom space up to the 64k (16-bit address) limit. cpu data memory the external cpu data memory space, if separated from program memory by the dm optional output, can be mapped anywhere from 0 to 64k (full 16-bit address space). data memory uses the same address/data bus (port 1) and additional addresses (chosen from port 0) as program memory. data memory is distin- guished from program memory by the dm pin (p3 5 ), and by the fact that data memory can begin at address ooooh. this feature differs from the z8.
cmos super8 romless mcu product specification ps014602-0103 instruction set 23 figure 16.program and data memory address spaces instruction set the super8 instruction set is designed to handle its large register set. the instruc- tion set provides a full complement of 8-bit arithmetic and logical operations, including multiply and divide. it supports bcd operations using a decimal adjust- ment of binary values, and it supports incrementing and decrementing 16-bit quantities for addresses and counters. it provides extensive bit manipulation, and rotate and shift operations, and it requires no special i/o instructions-the i/o ports are mapped into the register file. instruction pointer a special register called the instruction pointer (ip) provides hardware support for threaded-code languages. it consists of register-pair r218 and r219, and it con- tains, memory addresses. the msb is r218. threaded-code languages deal with an imaginary higher-level machine within the existing hardware machine. the ip acts like the pc for that machine. the com- mand next passes control to or from the hardware machine to the imaginary machine, and the commands enter and exit are imaginary machine equiva- lents of (real machine) calls and returns. if the commands next, enter, and exit are not used, the ip can be used by the fast interrupt processing, as described in the interrupts section. external data mem0ry external program mem0ry this boundary may be at 0, or 8192 depending on rom size 32 0 interrupt vectors program memory on-chip rom or protopack eprom 65535 65535 data memory
cmos super8 romless mcu product specification ps014602-0103 instruction set 24 flag register the flag register (flags) contains eight bits that describe the current status of the super8. four of these can be tested and used with conditional jump instruc- tions; two others are used for bcd- arithmetic. flags also contains the bank address bit and the fast interrupt status bit. the flag bits can be set and reset by instructions. do not specify flags as the destination of an instruction that normally affects the flag bits or the result is unspecified. the following paragraphs describe each flag bit: bank address . this bit is used to select one of the register banks (0 or 1) between (decimal) addresses 224 and 255. it is cleared by the sbo instruction and set by the sb1 instruction. fast interrupt status . this bit is set during a fast interrupt cycle and reset during the iret following interrupt servicing. when set, this bit inhibits all interrupts and causes the fast interrupt return to be executed when the iret instruction is fetched. half-carry . this bit is set to 1 whenever an addition generates a carry out of bit 3, or when a subtraction borrows out of bit 4. this bit is used by the decimal adjust (da) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (bcd) result. this flag, and the decimal adjust flag, are not usually accessed by users. decimal adjust . this bit is used to specify what type of instruction was executed last during bcd operations, so a subsequent decimal adjust operation can func- tion correctly. this bit is not usually accessible to programmers, and cannot be used as a test condition. overflow flag . this flag is set to 1 when the result of a twos-complement opera- tion was greater than 127 or less than -128. it is also cleared to o during logical operations. sign flag . following arithmetic, logical, rotate, or shift operations, this bit identi- fies the state of the msb of the result. a 0 indicates a positive number and a 1 indicates a negative number. zero flag . for arithmetic and logical operations, this flag is set to 1 if the result of the operation is zero. for operations that test bits in a register, the zero bit is set to 1 if the result is zero. for rotate and, shift operations, this bit is set to 1 if the result is zero. caution:
cmos super8 romless mcu product specification ps014602-0103 instruction set 25 carry flag . this flag is set to 1 if the result from an arithmetic operation generates a carry out of, or a borrow into, bit 7. after rotate and shift operations, it contains the last value shifted out of the speci- fied register. it can be set, cleared, or complemented by instructions. condition codes the flags c, z, s, and v are used to control the operation of conditional jump instructions. the opcode of a conditional jump contains a 4-bit field called the condition code (cc). this specifies under which conditions it is to execute the jump. for example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. the condition codes and their meanings are given in condition codes and mean- ings. addressing modes all operands except for immediate data and condition codes are expressed as register addresses, program memory addresses, or data memory addresses. the addressing modes and their designations are: ? register (r) ? indirect register (ir) ? indexed (x) ? direct (da) ? relative (ra) ? immediate (im) ? indirect (ia) table 18.condition codes and meanings binary mnemonic flags meaning 0000 f - always false 1000 - - always true 0111 1 c c = 1 carry 1111 1 nc c = 0 no carry
cmos super8 romless mcu product specification ps014602-0103 instruction set 26 registers can be addressed by an 8-bit address in the range of 0 to 255. working, registers can also be addressed using 4-bit addresses, where five bits contained in a register pointer (r218 or r219) are concatenated with three bits from the 4-bit address to form an 8-bit address. registers can be used in pairs to generate 16-bit program or data memory addresses. notation and encoding the instruction set notations are described in table 5. 0110 1 zz = 1 zero 1110 1 nz z = 0 not zero 1101 pl s = 0 plus 0101 mi s = 1 minus 0100 ov v = 1 overflow 1100 nov v = 0 no overflow 0110 1 eq z = 1 equal 1110 1 ne z = 0 not equal 1001 ge (s xor v)= 0 greater than or equal 0001 lt (s xor v)= 1 less than 1010 gt (z or (s xor v))= 0 greater than 0010 le (z or (s xor v))= 1 less than or equal 1111 1 uge c=0 unsigned greater than or equal 0111 1 ult c=1 unsigned less than 1011 ugt (c = 0 and z = 0)= 1 unsigned greater than 0011 ule (c or z)= 1 unsigned less than or equal 1. has condition codes that relate to two different mnemonics but test the same flags. for example, z and eq are both true if the zero flag is set, but after an add instruction, z would probably be used, while after a cp instruction, eq would probably be used. table 18.condition codes and meanings binary mnemonic flags meaning
cmos super8 romless mcu product specification ps014602-0103 instruction set 27 functional summary of commands figure 17 shows the formats followed by a quick reference guide to the com- mands. table 19.instruction set notations notation meaning notation meaning cc condition code (see table 4) da direct address (between 0 and 65535) r working register (between 0 and 15) ra relative address rb bit of working register im immediate r0 bit 0 of working register iml immediate long r register or working register dst destination operand rr register pair or working register pair (register always start on an even-number boundary) pairs src source operand @indirect ia indirect address sp stack ir indirect working register pc program ir indirect register or indirect working register ip irr indirect working register pair flags flags irr indirect register pair or indirect working register pair rp x indexed # immediate xs indexed, short offset % hexadecimal xl indexed, long offset opc opcode
cmos super8 romless mcu product specification ps014602-0103 instruction set 28 figure 17.instruction formats figure 18.instruction formats (continued) opc opc opc opc opc opc opc opc opc opc opc opc ccf, di, ei, enter, exit, iret, next, nop, r cc dst src dst dst dst dst dst dst dst dst dst src src src src b b 0 1 rcf, ret, sb0, sb1, scf, wfi adc, add, and, cp, ld, ldc, ldci, ldcd, inc lde, lded, or, sbc, sub, tcm, tm, xor ldc, ldcpd, ldcpi, lde, ldepd, ldepi call, da, dec, decw, inc, incw, jp, pop, rl, rlc,m rr, rrc, swap, clr, sra, com push, srp, srp0, srp1 bitc, bitr bits djnz jr ld ld one-byte instructions two-byte instructions adc, add, and, cp, ld, or, pushud, pushui, sbc, sub, tcm, tm, xor adc, add, and, cp, div, ld, ldw, mult, or, popud, popui, sbc, sub, tcm, tm, xor band, bcp, bor, bxor, db band, bor, btjrt, bxor, ldb btjrf cpije, cpijne ld, ldc, lde ld, ldc, lde jp call opc opc opc opc opc opc opc opc opc opc opc opc opc opc opc opc opc opc cc dst src dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst 0 x ra x src b src src b 1 0 b src src src src src src src src src src src src src 0000 0000 0001 0001 x 0 or 1 x 0 or 1 ldc, lde ldc, lde ldc lde ldc lde ldw for ldc, x = even for lde, x = odd } three-byte instructions four-byte instructions
cmos super8 romless mcu product specification ps014602-0103 instruction summary 29 instruction summary table 20.instruction summary instruction and operation address mode opcode byte (hex) flags affected dst src cz svdh adc dst, src note 1 1[ ] * * * - 0 * dst dst + src +c add dst, src note 1 0[ ] * * * * 0 * dst dst + src and dst, src note 1 5[ ] - * * 0 - - dst dst and src band dst, src r0 rb 67 - * 0 u - - dst dst and src rb r0 67 bcp dst, src r0 rb 17 - * 0 u - - dst ? src bitc dst rb 57 - * 0 u - - dst dst bitr dst rb 77 ------ dst bits dst rb 77 ------ dst bor dst, src r0 rb 07 - * 0 u - - dst dst or src rb r0 btjrf ra rb 37 ------ if src = 0, pc = pc + dst btjrt ra rb 37 ------ if src = ?1, pc = pc + dst bxor dst, src r0 rb 27 - * 0 u - - dst dst xor src rb r0 27 call dst da f6 ------
cmos super8 romless mcu product specification ps014602-0103 instruction summary 30 sp sp-2 irr f4 @sp pc, ia d4 pc dst ccf ef *----- c not c clr dst r b0 ------ dst 0ir b1 com dst r 60 - * * 0 - - dst not dst ir 61 cp dst, src note 1 a[ ] * * * * - - dst - src cpije r ir c2 ------ if dst ? src = 0, then pc pc + ra ir ir + 1 cpijne r ir d2 ------ if dst ? src = 0, then pc pc + ra ir ir + 1 da dst r 40 * * * u - - dst da dst ir 41 dec dst r 00 - * * * - - dst dst -1 ir 01 decw dst rr 80 - * * * - - dst dst-1 ir 81 di 8f ------ table 20.instruction summary (continued) instruction and operation address mode opcode byte (hex) flags affected dst src cz svdh
cmos super8 romless mcu product specification ps014602-0103 instruction summary 31 smr(0) 0 div dst, src dst src rr r 94 ****-- dst (upper) quotient rr ir 95 dst (lower) remaind er rr im 96 djnz r, dst ra r ra ------ r r - 1 (r = 0 to f) if r 0 pc pc + dst ei 9f ------ smr(0) 1 enter 1f ------ sp sp - 2 @sp ip ip pc pc @ip ip ip + 2 exit 2f ------ ip @sp sp sp + 2 pc @ip ip ip + 2 inc dst r re - * * * - - dst dst + 1 (r = 0 to f) r20 ir 21 table 20.instruction summary (continued) instruction and operation address mode opcode byte (hex) flags affected dst src cz svdh
cmos super8 romless mcu product specification ps014602-0103 instruction summary 32 incw dst rr a0 - * * * - - dst
dst ir a1 iret (fast) bf restored to before interrupt pc ip flag flag? fis 0 iret (normal) bf restored to before interrupt flags @sp; sp sp + 1 pc @sp; sp sp + 2; smr(0) 1 jp cc, dst da ccd ------ if cc is true, (cc = 0 to f) pc dst irr 30 jr cc, dst ra ccb ------ if cc is true, pc pc + d (cc = 0 to f) ld dst, src r im rc ------ dst src r r r8 rr r9 (r = 0 to f) rirc7 ir r d7 rr e4 rir e5 rim e6 ir im d6 ir r f5 rx87 xr 97 table 20.instruction summary (continued) instruction and operation address mode opcode byte (hex) flags affected dst src cz svdh
cmos super8 romless mcu product specification ps014602-0103 instruction summary 33 ldb dst, src r0 rb 47 ------ dst src rb r0 47 ldc/lde r irr c3 ------ dst src irr r d3 rxse7 xs r f7 rx1a7 x1 r b7 rdaa7 da r b7 ldcd/lded dst, src r irr e2 ------ dst src rr rr - 1 ldei/ldci dst, srcr irr e3 ------ dst src rr rr + 1 ldcpd/ldepd dst, src rr rr - 1 irr r f2 ------ dst src ldcpi/ldepi dst, src rr rr + 1 irr r f3 ------ dst src ldw dst, src rr r c4 ------ dst src rr ir c5 rr im c6 mult dst, src rr r 84 ------ table 20.instruction summary (continued) instruction and operation address mode opcode byte (hex) flags affected dst src cz svdh
cmos super8 romless mcu product specification ps014602-0103 instruction summary 34 dst src rr ir 85 rr im 86 next 0f ------ pc @ip ip ip + 2 nop ff ------ or dst, src note 1 4[ ] - * * 0 - - dst dst or src pop dst r 50 ------ dst @sp; ir 51 sp sp + 1 popud dst, src r ir 92 ------ dst src ir ir - 1 popui dst, src r ir 93 ------ dst src ir ir + 1 push src r 70 ------ sp sp - 1; @sp src ir 71 pushud dst, srcir r 82 ------ ir ir - 1 dst src pushui dst, src ir r 83 ------ ir ir + 1 dst src rcf cf 0----- c 0 ret af ------ table 20.instruction summary (continued) instruction and operation address mode opcode byte (hex) flags affected dst src cz svdh
cmos super8 romless mcu product specification ps014602-0103 instruction summary 35 pc @sp; sp sp + 2 rl dst r 90 * * * * - - c dst(7) ir 91 dst(0) dst(7) dst(n + 1) dst(n) n = 0 to 6 rlc dst r 10 * * * * - - dst(0) cir 11 c dst(7) dst(n + 1) dst(n) n = 0 to 6 rr dst r e0 ****-- c dst(0) ir e1 dst(7) dst(0) dst(n) dst(n + 1 ) n = 0 to 6 rrc dst r c0 ****-- c dst(0) ir c1 dst(7) c dst(n) dst(n + 1 ) n = 0 to 6 sb0 4f ------ bank 0 sb1 5f ------ bank 1 sbc dst, src note 1 3[ ] * * * * 1 * dst dst src c scf df 1----- table 20.instruction summary (continued) instruction and operation address mode opcode byte (hex) flags affected dst src cz svdh
cmos super8 romless mcu product specification ps014602-0103 instruction summary 36 c 1 sra dst r d0 * * * 0 - - dst(7) dst(7) ir d1 c dst(0) dst(n) dst(n + 1 ) n = 0 to 6 srp src im 31 ------ rp0 im rp0 im + 8 srp0 im 31 ------ rp0 im srp1 im 31 ------ rp1 im sub dst, src note 1 2[ ] * * * * 1 * dst dst src swap dst r f0 - * * u - - dst(0-3) dst(4-7) ir f1 tcm dst, src note 1 6[ ] - * * 0 - - (not dst) and src tm dst, src note 1 7[ ] - * * 0 - - dst and src wfi 3f ------ xor dst, src note 1 b[ ] - * * 0 - - dst dst xor src 1. these instructions have an identical set of addressing modes, which are encoded for brevity. the first opcode nibble identifies the command, and is found in the table above. the second nibble, represented by a [ ], defines the addressing mode as shown in table 6. table 20.instruction summary (continued) instruction and operation address mode opcode byte (hex) flags affected dst src cz svdh
cmos super8 romless mcu product specification ps014602-0103 instruction summary 37 table 21.second nibble addr mode lower opcode nibble 1 1. for example, to use an opcode represented as x[ ] with an "rr" addressing mode, use the opcode "x4." 0= cleared to zero 1= set to one -= unaffected *= set or reset, depending on result of operation. u= undefined dst src rr[2] rir[3] rr[4] rir[5] rim[6]
cmos super8 romless mcu product specification ps014602-0103 super-8 opcode map 38 super-8 opcode map figure 19.opcode map 6 dec r 1 6 dec ir 1 6 add r 1 ,r 2 6 add r 1 ,ir 2 10 add r 2 ,r 1 10 add ir 2 ,r 1 10 add r 1 ,im 10 bor* r 0 -r b 6 ld r 1 ,r 2 6 ld r 2 ,r 1 12/10 djnz r 1 ,ra 12/10 jr cc,ra 6 ld r 1 ,rm 12/10 jp cc,da 6 inc r 1 14 next 6 rlc r 1 6 rlc ir 1 6 adc r 1 ,r 2 6 adc r 1 ,ir 2 10 add r 2 ,r 1 10 adc ir 2 ,r 1 10 adc r 1 ,im 10 bcp r 1 ,b,r 2 6 inc r 1 6 inc ir 1 6 sub r 1 ,r 2 6 sub r 1 ,ir 2 10 sub r 2 ,r 1 10 sub ir 2 ,r 1 10 sub r 1 ,im 10 bxor* r 0 -r b 6 da r 1 6 da ir 1 6 or r 1 ,r 2 6 or r 1 ,ir 2 10 or r 2 ,r 1 10 or ir 2 ,r 1 10 or r 1 ,im 10 ldb* r 0 -rb 6 com r 1 6 com ir 1 6 tcm r 1 ,r 2 6 tcm r 1 ,ir 2 10 tcm r 2 ,r 1 10 tcm ir 2 ,r 1 10 tcm r 1 ,im 10 band* r 0 -rb 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 jp irr 1 note c 6 sbc r 1 ,r 2 6 sbc r 1 ,ir 2 10 sbc r 2 ,r 1 10 sbc ir 2 ,r 1 10 sbc r 1 ,im note a 10/12 push r 2 6 tm r 1 ,r 2 6 tm r 1 ,ir 2 10 tm r 2 ,r 1 10 tm ir 2 ,r 1 10 tm r 1 ,im note b 12/14 push ir 2 10 pop r 1 10 pop ir 1 6 and r 1 ,r 2 6 and r 1 ,ir 2 10 and r 2 ,r 1 10 and ir 2 ,r 1 10 and r 1 ,im 10 bitc r 1 ,b 10 decw irr 1 10 decw ir 1 10 pushud ir 1 ,r 2 10 pushui ir 2 ,r 2 24 mult r 2 ,rr 1 24 mult ir 2 ,rr 1 24 mult im,rr 1 10 ld r 1 ,x,r 2 6 rl r 1 6 rl ir 1 6 popud ir 2 ,r 1 6 popui ir 2 ,r 1 28/12 div r 2 ,rr 1 28/12 div ir 2 ,rr 1 28/12 div im,rr 1 10 ld r 2 ,x,r 1 10 incw rr 1 6 cp r 1 ,r 2 6 cp r 1 ,ir 2 10 cp r 2 ,r 1 10 cp ir 2 ,r 1 10 cp r 1 ,im note d 10 incw ir 1 6 clr r 1 6 clr ir 1 6 xor r 1 ,r 2 6 xor r 1 ,ir 2 10 xor r 2 ,r 1 10 xor ir 2 ,r 1 10 xor r 1 ,im note e 6 rrc irr 1 6 rrc ir 1 16/18 cpije ir,r 2 ,ra 12 ldc* r 1 ,irr 2 10 ldw rr 2 ,rr 1 10 ldw ir 2 ,rr 1 12 ldw rr 1 ,iml 6 ld r 1 ,ir 2 6 sra r 1 6 sra ir 1 16/18 cpijne ir 1 ,r 2 ,ra 12 ldc* r 2 ,irr 1 20 call ia 1 10 ld ir 1 ,im 6 ld ir1,r 2 6 rr r 1 6 rr ir 1 16 ldcd* r 1 ,irr 2 16 ldci* r 1 ,irr 2 10 ld r 2 ,r 1 10 ld ir 2 ,r 1 10 ld r 1 ,im 18 ldc* r 1 ,irr 2 ,xs 8 swap r 1 8 swap ir 1 16 ldcpd* r 2 ,irr 1 16 ldcpi* r 2 ,irr 1 18 call irr 1 18 call r 2 ,ir 1 18 call da 1 18 ldc* r 1 ,irr 1 ,xs 6 wfi 20 enter 22 exit 14 ret 16/6 iret 6 rcf 6 scf 6 ccf 6 nop 6 sbo 6 sbi 6 ei 6 di 0 123 4 56 78 9 a b cdef lower nibble (hex) upper nibble (hex) note a note b note a note c note e note d 16/18 btjrf r 2 ,b,ra 16/18 btjrt r 2 ,b,ra 8 bitr r 1 ,b 8 bits r 1 ,b 6 srp im 6 srp0 im 6 srp1 im 20 ldc* r 1 ,irr 2 ,xl 20 ldc* r 1 ,da 2 20 ldc* r 2 ,irr 2 ,xl 20 ldc* r 2 ,da 1 legend: r = 4-bit address r = 8-bit address b = bit number r 1 or r 1 = dsts address r 2 or r 2 = src address *examples: borr 0 -r 2 is borr 1 ,b,r 2 or borr 2 ,b,r 1 ldcr 1 ,irr 2 is ldcr 1 ,irr 2 = program or lder 1 ,irr 2 = data sequence: opcode, first, second, third operands note: the blank areas are not defined.
cmos super8 romless mcu product specification ps014602-0103 instructions 39 instructions table 22.super8 instructions mnemonic operands instruction load instructions clr dst clear ld dst, src load ldb dst, src load bit ldc dst, src load program memory lde dst, src load data memory ldcd dst, src load program memory and decrement lded dst, src load data memory and decrement ldci dst, src load program memory and increment ldei dst, src load data memory and increment ldcpd dst, src load program memory with pre-decrement ldepd dst, src load data memory with pre-decrement ldcpi dst, src load program memory with pre-increment ldepi dst, src load data memory with pre-increment ldw dst, src load word pop dst pop stack popud dst, src pop user stack (decrement) popui dst, src pop user stack (increment) push src push stack pushud dst, src push user stack (decrement) pushui dst, src push user stack (increment) arithmetic instructions adc dst, src add with carry add dst, src add cp dst, src compare da dst decimal adjust dec dst decrement
cmos super8 romless mcu product specification ps014602-0103 instructions 40 decw dst decrement word div dst, src divide inc dst increment incw dst increment word mult dst, src multiply sbc dst, src subtract with carry sub dst, src subtract logical instructions and dst, src logical and com dst complement or dst, src logical or xor dst, src logical exclusive program control instructions btjrt dst, src bit test jump relative on true btjrf dst, src bit test jump relative on false call dst call procedure cpije dst, src compare, increment and jump on equal cpijne dst,src compare, increment and jump on non-equal djnz r, dst decrement and jump on non-zero enter enter exit exit iret return from interrupt jp cc, dst jump on condition code jp dst jump unconditional jr cc, dst jump relative on condition code jr dst jump relative unconditional next next ret return wfi wait for interrupt table 22.super8 instructions (continued) mnemonic operands instruction
cmos super8 romless mcu product specification ps014602-0103 instructions 41 bit manipulation instructions band dst,src bit and bcp dst, src bit compare bitc dst bit complement bitr dst bit reset bits dst bit set bor dst, src bit or bxor dst, src bit exclusive or tcm dst, src test complement under mask tm dst, src test under mask rotate and shift instructions rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic swap dst swap nibbles cpu control instructions ccf complement carry flag di disable interrupts ei enable interrupts nop do nothing rcf reset carry flag sb0 set bank 0 sb1 set bank 1 scf set carry flag srp src set register pointers srp0 src set register pointer zero table 22.super8 instructions (continued) mnemonic operands instruction
cmos super8 romless mcu product specification ps014602-0103 interrupts 42 interrupts the super8 interrupt structure contains 8 levels of interrupt, 16 vectors, and 27 sources. interrupt priority is assigned by level, controlled by the interrupt priority register (ipr). each level is masked (or enabled) according to the bits in the interrupt mask register (imr), and the entire interrupt structure can be disabled by clearing a bit in the system mode register (r222). the three major components of the interrupt structure are sources, vectors, and levels. these are shown in figure 20 and discussed in the following paragraphs. sources a source is anything that generates an interrupt. this can be internal or external to the super8 mcu. internal sources are hardwired to a particular vector and level, while external sources can be assigned to various external events. vectors the 16 vectors are divided unequally among the eight levels. for example, vector 12 belongs to level 2, while level 3 contains vectors 0, 2, 4, and 6. the vector number is used to generate the address of a particular interrupt servic- ing routine; therefore all interrupts using the same vector must use the same inter- rupt handling routine. levels levels provide the top level of priority assignment. while the sources and vectors are hardwired within each level, the priorities of the levels can be changed by using the interrupt priority register (see figure 15 for bit details). if more than one interrupt source is active, the source from the highest priority level is serviced first. if both sources are from the same level, the source with the lowest vector has priority. for example, if the uart receive data bit and uart parity error bit are both active, the uart parity error bit is serviced first because it is vector 16, and uart receive data is vector 20. srp1 src set register pointer one table 22.super8 instructions (continued) mnemonic operands instruction
cmos super8 romless mcu product specification ps014602-0103 interrupts 43 the levels are shown in figure 20. figure 20.interrupt levels and vectors enables ? interrupts can be enabled or disabled as follows: ? interrupt enable/disable. the entire interrupt structure can be enabled or disabled by setting bit 0 in the system mode register (r222). ? level enable. each level can be enabled or disabled by setting the appropriate bit in the interrupt mask register (r221). ? level priority. the priority of each level can be controlled by the values in the in- terrupt priority register (r255, bank 0). ? source enable/disable. each interrupt source can be enabled or disabled in the sources? mode and control register. polling vectors levels polling irq2 irq5 irq4 irq7 irq3 irq0 irq6 irq1 12 14 28 30 0 2 4 6 8 10 16 18 20 22 24 26 interupt sources counter 0 zero count external interrupt (p2 6 ) external interrupt (p2 7 ) counter 1 zero count external interrupt (p3 6 ) external interrupt (p3 7 ) handshake channel 0 external interrupt (p2 4 ) external interrupt (p2 5 ) handshake channel 1 external interrupt (p3 4 ) external interrupt (p3 5 ) reserved reserved external interrupt (p3 2 ) external interrupt (p2 2 ) external interrupt (p2 3 ) external interrupt (p3 3 ) uart receive overrun uart framing error uart parity error uart wakeup detect uart break detect uart control char detect uart receive data external interrupt (p3 0 ) uart zero count external interrupt (p2 1 ) uart transmit data external interrupt (p3 1 ) external interrupt (p20)
cmos super8 romless mcu product specification ps014602-0103 interrupts 44 service routines before an interrupt request can be granted, a) interrupts must be enabled, b) the level must be enabled, c) it must be the highest priority interrupting level, d) it must be enabled at the interrupting source, and e) it must have the highest priority within the level. if all this occurs, an interrupt request is granted. the super8 then enters an interrupt machine cycle that completes the following sequence: ? it resets the interrupt enable bit to disable all subsequent interrupts. ? it saves the program counter and status flags on the stack. ? it branches to the address contained within the vector location for the interrupt. ? it passes control to the interrupt servicing routine. when the interrupt servicing routine has serviced the interrupt, it should issue an interrupt return (iret) instruction. this restores the program counter and status flags and sets the interrupt enable bit in the system mode register. fast interrupt processing the super8 provides a feature called fast interrupt processing, which completes the interrupt servicing in 6 clock periods instead of the usual 22. two hardware registers support fast interrupts. the instruction pointer (ip) holds the starting address of the service routine, and saves the pc value when a fast interrupt occurs. a dedicated register, flag?, saves the contents of the flags register when a fast interrupt occurs. to use this feature, load the. address of the service routine in the instruction pointer, load the level number into the fast interrupt select field, and turn on the fast interrupt enable bit in the system mode register. when an interrupt occurs in the level selected for fast interrupt processing, the fol- lowing occurs: ? the contents of the instruction pointer and program counter are swapped. ? the contents of the flag register are copied into flag?. ? the fast interrupt status bit in flags is set. ? the interrupt is serviced. ? when iret is issued after the interrupt service outline is completed, the instruc- tion pointer and program counter are swapped again.
cmos super8 romless mcu product specification ps014602-0103 stack operation 45 ? the contents of flag? are copied back into the flag register ? the fast interrupt status bit in flags is cleared. the interrupt servicing routine selected for fast processing should be written so that the location after the iret instruction is the entry point the next time the (same) routine is used. level or edge triggered because internal interrupt requests are levels and interrupt requests from the out- side are (usually) edges, the hardware for external interrupts uses edge-triggered flip-flops to convert the edges to levels. the level-activated system requires that interrupt-serving software perform some action to remove the interrupting source. the action involved in serving the inter- rupt may remove the source, or the software may have to actually reset the flip- flops by writing to the corresponding interrupt pending register. stack operation the super8 architecture supports stack operations in the register file or in data memory. bit 1 in the external memory timing register (r254 bank 0) selects between the two. register pair 216-217 forms the stack pointer used for all stack operations. r216 is the msb and r217 is the lsb. the stack pointer always points to data stored on the top of the stack. the address is decremented prior to a push and incremented after a pop. the stack is also used as a return stack for calls and interrupts. during a call, the contents of the pc are saved on the stack, to be restored later. interrupts cause the contents of the pc and flags to be saved on the stack, for recovery by iret when the interrupt is finished. when the super8 is configured for an internal stack (using the register file), r217 contains the stack pointer. r216 may be used as a general-purpose register, but its contents are changed if an overflow or underflow, occurs as the result of incre- menting or decrementing the stack address during normal stack operations. user-defined stacks the super8 provides for user-defined stacks in both the register file and program or data memory. these can be made to increment or decrement on a push by the choice of opcodes. for example, to implement a stack that grows from low
cmos super8 romless mcu product specification ps014602-0103 counter/timers 46 addresses to high addresses in the register file, use pushui and popud. for a stack that grows from high addresses to low addresses in data memory, use ldei for pop and ldepd for push. counter/timers the super8 has two identical independently programmable 16-bit counter/timers that can be cascaded to produce a single 32-bit counter. they can be used to count external events, or they can obtain their input internally. the internal input is obtained by dividing the crystal frequency by four. the counter/timers can be set to count up or down, by software or external events. they can be set for single or continuous cycle counting, and they can be set with a bi-value option, where two preset time constants alternate in loading the counter each time it reaches zero. this can be used to produce an output pulse train with a variable duty cycle. the counter/timers can also be programmed to capture the count value at an external event or generate an interrupt whenever the count reaches zero. they can be turned on and off in response to external events by using a gate and/or a trigger option. the gate option enables counts only when the gate line is low; the trigger option turns on the counter after a transient high. the gate and trigger options used together cause the counter/timer to work in gate mode after initially being triggered. the control and status register bits for the counter/timers are shown in figure 7. dma the super8 features an on-chip direct memory access (dma) channel to provide high bandwidth data transmission capabilitie s. the dma channel can be used by the uart receiver, uart transmitter, or handshake channel 0. data can be trans- ferred between the peripheral and contiguous locations in either the register file or external data memory. a 16-bit count register determines the number of transac- tions to be performed; an interrupt can be generated when the count is exhausted. dma transfers to or from the register file require six cpu clock cycles; dma trans- fers to or from external memory take ten cpu clock cycles, excluding wait states.
cmos super8 romless mcu product specification ps014602-0103 absolute maximum ratings 47 absolute maximum ratings stresses greater than these may cause permanent damage to the device. this is a stress rating only; operation of the device under conditions more severe than those listed for operating conditions may cause permanent damage to the device. exposure to absolute maximum ratings for extended periods may also cause per- manent damage. standard test conditions figure 21 shows the setup for standard test conditions. all voltages are refer- enced to ground, and positive current flows into the reference pin. standard conditions are: ? + 4.75 v vcc + 5.25v ? gnd = 0 v ? 0c ta + 70c figure 21.standard test load voltage on all pins with respect to ground -0.3 v to+7.0 v ambient operating temperature see ordering information storage temperature -65 c to + 150 c from output under test test load (for all pins) +5 v 1k 150pf 400 a
cmos super8 romless mcu product specification ps014602-0103 dc characteristics 48 dc characteristics input handshake timing figure 22.fully interlocked mode table 23.dc characteristics symbol parameter min max unit condition v ch clock input high voltage 3.8 v cc v driven by external clock generator v cl clock input low voltage -0.3 0.8 v driven by external clock generator v ih input high voltage 2.2 v cc v v il input low voltage -0.3 0.8 v v rh reset input high voltage 3.8 v cc v v rl reset input low voltage -0.3 0.8 v v oh output high voltage 2.4 v i oh = -400 a v ol output low voltage 0.4 v i ol = +4.0 ma i il input leakage -10 10 a i ol output leakage -10 10 a i ir reset input current -50 a i cc vcc supply current 320 rna 5 2 4 1 3 7 data in dav in rdy out
cmos super8 romless mcu product specification ps014602-0103 ac characteristics (20 mhz) 49 figure 23.strobed mode ac characteristics (20 mhz) input handshake table 24.ac characteristics (20 mhz) input handshake number symbol parameter min max notes 1,2 1. times are preliminary and subject to change. 2. times given are in ns. 1 tsdi(dav) data in to setup time 0 2 tddavif(rdy) dav input to rdy delay 200 note 3 3. standard test load 3 thdi(rdy) data in hold time from rdy 0 4 twdav dav in width 45 5 thdi(dav) data in hold time from dav 130 6tddav(rdy)dav input to rdy delay 100 note 4 4. this time assumes user program reads data before dav input goes high. rdy does not go high before data is read. 7 tdrdyf(dav) rdy output to dav delay 0 5 4 1 data in dav in
cmos super8 romless mcu product specification ps014602-0103 output handshake timing 50 output handshake timing figure 24.fully interlocked mode figure 25.strobed mode ac characteristics (12 mhz, 20 mhz) output handshake table 25.ac characteristics (12 mhz, 20 mhz) output handshake number symbol parameter min max notes 1,2 1. times are preliminary and subject to change. 2. times given are in ns. 1 tddo(dav) data out to dav delay 90 note 3,4 3. standard test load 4. time given is for zero value in deskew counter. for nonzero valu e of n where n = 1, 2,. . . 15 add 2 x n x tpc to the given t ime. 2 tdrdyr(dav) rdy input to dav delay 0 110 note 3 3 tddavof(rdy) dav output to rdy delay 0 4 tdrdyf(dav) rdy input to dav delay 0 110 note 3 5 tddavor(rdy) dav output to rdy delay 0 6 twdavo dav output width 150 note 4 dav out data out rdy in 5 2 3 1 4 dav out data out 1 6
cmos super8 romless mcu product specification ps014602-0103 ac characteristics (12 mhz) 51 ac characteristics (12 mhz) read /write table 26.ac characteristics (12 mhz) read/write normal timing extended timing number symbol parameter min max min max notes 1,2 1. all times are in ns and are for 12 mhz input frequency. 2. timings are preliminary and subject to change 3.) wait states add 167 ns to these times. 4.) auto-wait states add 167 ns to this time.. 1 tda(as) address valid to as delay 35 115 2 tdas(a) as to address float delay 65 150 3 tdas(dr) as to read data required valid 270 600 note 3 4twasas low width 65 150 5 tda(ds) address float to ds 20 20 6a twds(read) ds (read) low width 225 470 note 3 6b twds(write) ds (write) low width 130 295 1 note 3 7 tdds(dr) ds to read data required valid 180 420 note 3 8 thds(dr) read data to ds hold time 0 0 9tdds(a)ds to address active delay 50 135 10 tdds(as) ds to as delay 60 145 11 tddo(ds) write data valid to ds (write) delay 35 115 12 tdas(w) as to wait delay 220 600 note 4 13 thds(w) ds to wait hold time 0 0 14 tdrw(as) r/w valid to as delay 50 135
cmos super8 romless mcu product specification ps014602-0103 ac characteristics (20 mhz) 52 ac characteristics (20 mhz) read /write table 27.ac characteristics (20 mhz) read/write normal timing extended timing number symbol parameter min max min max notes 1,2 1. all times are in ns and are for 20 mhz input frequency. 2. timings are preliminary and subject to change. 3.) wait states add 100 ns to these times. 4.) auto-wait states add 100 ns to this time 1 tda(as) address valid to as delay 20 50 2 tdas(a) as to address float delay 35 85 3 tdas(dr) as to read data required valid 150 335 note 3 4twasas low width 35 85 5 tda(ds) address float to ds 00 6a twds(read) ds (read) low width 125 275 note 3 6b twds(write) ds (write) low width 65 165 note 3 7 tdds(dr) ds to read data required valid 80 225 note 3 8 thds(dr) read data to ds hold time 0 0 9tdds(a)ds to address active delay 20 70 10 tdds(as) ds to as 1 delay 30 80 11 tddo(ds) write data valid to ds (write) delay 10 50 12 tdas(w) as to wait delay 90 335 note 4 13 thds(w) ds to wait hold time 0 0 14 tdrw(as) r/w valid to as delay 20 70
cmos super8 romless mcu product specification ps014602-0103 ac characteristics (20 mhz) 53 figure 26.external memory read and write timing figure 27.eprom read timing 1 7 14 10 9 11 12 4 1 2 6 5 13 r/w port 0 dm port 1 as cs wait d 0 -d 7 a 8 -a 15 , dm d 0 -d 7 , out a 0 -a 7 8 out in wait window 1 d 0 -d 7 in a 0 -a 13 address out data in
cmos super8 romless mcu product specification ps014602-0103 ac characteristics (20 mhz) 54 ac characteristics (20 mhz) eprom read cycle example: packaging information figure 28.44-pin plcc table 28.ac characteristics (20 mhz) eprom read cycle number symbol parameter min max notes 1,2 1. all times are in ns and are for 12 mhz input frequency. 2. timings are preliminary and subject to change. 3.) wait states add 167 ns to these times. 1 tda(dr) address valid to read data required valid 170 note 3
cmos super8 romless mcu product specification ps014602-0103 packaging information 55 figure 29.48-pin dip

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